It is known to combine different functional blocks on a single IC chip for density and cost advantages. However, improvements in circuit density may cause the parasitic resistance and capacitance of the device to increase. Memory and logic components are generally formed using different process technologies to enhance the performance of each individual component. Therefore, to effectively integrate distinct functional blocks, the overall manufacturing process must be modified without introducing significant complexity.
Several processes for incorporating a metal-insulator-metal (MIM) capacitor into an embedded DRAM (eDRAM) system are known. Typically, a MIM capacitor is inserted between the silicon substrate and the first metal layer. This configuration is usually preferred because it offers smaller memory cells than designs having a MIM capacitor over the first metal layer. However, this type of fabrication results in an elongated contact between the first metal layer and substrate. As a result, taller contacts or vias increase the resistance (R) for a specific contact as well as the parasitic capacitance (C) between contact pairs. With the continued scaling of integrated circuits, routing wires are more closely packed leading to an increase in the parasitic capacitance (C) between the interconnect metal and adjacent metal layers. Scaling also reduces the dimensions of the routing wires leading to an increase in the interconnect resistance (R). Consequently, scaling and current fabrication processes increase the interconnect RC, which contributes to slower logic speeds. Therefore, current eDRAM processes are unsuitable for fabricating a high-performance SoC (system on a chip). Similarly, increased via resistance and capacitance reduce speeds in eDRAM systems having MIM capacitors between two metal layers. Therefore, a need exists for an improved process for manufacturing eDRAM systems that contain a MIM capacitor.